This application is related to Japanese Patent Application No. 2001-27117 filed on Feb. 2, 2001, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a method of producing a SOI (silicon-on-insulator) MOSFET (metal oxide semiconductor field effect transistor), more particularly, to a method of producing a SOI MOSFET with reduced electrical characteristic fluctuations related to variations in the thickness of a top semiconductor layer (i.e., an active semiconductor layer) and a MOSFET.
2. Description of Related Art
Generally known MOSFETs formed on SOI substrates such as SOS (silicon on sapphire), SIMOX (silicon separation by ion implantation of oxygen) and BSOI (bonded SOI) substrates have advantages in low-voltage and high-speed operation. In addition to that, the SOI MOSFETs have an advantage over devices formed on bulk silicon substrates in that layout area for the SOI MOSFETs is smaller.
However, the SOI MOSFETs have only three terminals (gate, drain and source) while bulk silicon MOSFETs have four terminals (gate, drain, source and substrate). For this reason, the SOI MOSFETs are inferior in electrical characteristics, especially, short channel effect, drain/source blocking voltage, punch through and the like.
Referring to FIGS. 10(a) and 10(b), in a bulk silicon MOSFET, the base terminal of a parasite bipolar (NPN) transistor is tied to the substrate and the substrate-source junction is reversely biased. As a result, if an impact ion current Ii is generated near a drain region, the parasite bipolar transistor has very little effect on operation of the MOSFET.
In contrast, referring to FIGS. 9(a) and 9(b), in a SOI MOSFET, the base terminal of a parasite bipolar transistor is a top semiconductor layer in a floating state. As a result, in usual operation, an impact ion current Ii generated near a drain region acts as a base current of the parasite bipolar transistor to generate a positive feed-back effect, which results in reduction in the short-channel effect and decrease in the drain/source blocking voltage. In the case where a channel region is formed in a relatively thick top semiconductor layer, the channel region behaves in a partially depleted mode and a so-called kink effect is produced in output characteristics owing to impact-ionization. Therefore, the electrical characteristics of the SOI MOSFET are significantly affected.
Here, the kink is a phenomenon in which majority carriers generated by impact ionization accumulate to raise the potential of the floating substrate, bring down threshold voltage and further cause drain current to increase abruptly. Thus the operation of the SOI MOSFET is greatly affected.
In order to realize a fully depleted SOI free of the kink effect, there is a technique of forming a top silicon layer which is thinner than a depletion layer induced by the gate electrode. Generally, as shown in FIG. 11, the full depletion of the top silicon layer requires adjustment of the thickness of the top silicon layer and the impurity concentration Na in the substrate.
However, as understood from FIG. 11, a major drawback of the fully depleted SOI transistor is that the threshold voltage Vth is sensitive to the thickness of the top silicon layer.
That is, the threshold is represented by                                                         Vth              ≅                              xe2x80x83                            ⁢                                                V                  fbt                                +                                                      q                    ·                    Na                    ·                    Tsi                                                        C                    tox                                                  +                                  2                  ·                                                                                                                        xe2x80x83                            ⁢                                                Φ                  F                                -                                                                            C                      box                                                              C                      tox                                                        ⁢                                      (                                                                  V                        sub                                            -                                              V                        fbb                                                              )                                                                                                                                                            Δ                  ⁢                                      xe2x80x83                                    ⁢                  Vth                                                  Δ                  ⁢                                      xe2x80x83                                    ⁢                  Tsi                                            ≅                              xe2x80x83                            ⁢                                                                    q                    ·                    Na                                                        C                    tox                                                  .                                                                        (        1        )            
wherein Vfbt is flat band voltage (at the top of the top silicon layer), Vfbb is flat band voltage (at the bottom of the top silicon layer), Ctox is capacity of a gate insulating film, Na is impurity concentration in the substrate, Tsi is thickness of the top silicon layer, xcfx86F is Fermi potential and Vsub is substrate voltage. For typical values of Na and the thickness of the gate insulating film, xcex94Vth/xcex94Tsi is about 10 mV/nm.
The threshold voltage affects or is related to electrical parameters such as OFF-state current which exponentially depends on the threshold voltage, as shown in the following formula:       I    doff    ≅      Io    ·    W    ·          10              (                  -                      Vth            S                          )            
wherein W is channel width of the transistor and I0 is a constant when the gate voltage is OV (I0=about 10xe2x88x927 A/xcexcm).
For example, with a fully depleted SOI transistor (slope S (S factor) in a sub-threshold region is about 65 mV/dec), the OFF current varies 10 times if the threshold voltage changes by 65 mV. Thus, to control the threshold voltage is important for the characteristics of the semiconductor device.
In 1995 IEEE International SOI Conference Short Course, there was proposed a method for suppressing variations in the threshold of the SOI MOSFET using a constant dose method. In the constant dose method, ion implantation is carried out on the top silicon layer of the SOI substrate under such conditions that the dose D=Naxc3x97Tsi is constant. As a result, it is understood from Formula (1) that the change of the threshold voltage Vth with respect to the thickness Tsi of the top silicon layer is suppressed. This is also clear from the relationship of Tsi to Vth shown in FIG. 12.
To suppress the dependency of Vth on Tsi, there is proposed a method of combining a partially depleted SOI and a fully depleted SOI as shown in FIG. 13 (Japanese Unexamined Patent Publication HEI 6(1994)-268215). In this device, the impurity concentration is higher at a channel edge 11 than at channel center 12 in the top silicon layer, and thereby, the channel edge 11 is not fully depleted but the channel center 12 is fully depleted. As a result, the threshold voltage of the SOI transistor is determined by the impurity concentration at the channel edge, and this device operates as a partially depleted device.
U.S. Pat. No. 5,841,170 discloses a SOI MOSFET whose channel region has an impurity profile that is nonuniform in a source/drain direction. This device is designed to have impurity concentrations such that full depletion is realized both at the channel center and at the channel edge. Thus, this device operates in a fully depleted mode and prevents the kink effect.
However, although the dependency of Vth on the thickness of the top silicon layer can be reduced by the constant dose method, the short-channel effect and the punch through are not considered. Since the impurity implantation is uniformly performed over the channel, the short-channel effect is more easily induced to take place.
The structure of the device proposed by Japanese Unexamined Patent Publication No. HEI 6(1994)-268215 can reduce the short-channel effect, but since the device operates in a partially depleted mode, the device is more susceptible to the kink effect and floating substrate effect.
The device proposed by U.S. Pat. No. 5,841,170 does not give any consideration to fluctuations in electrical characteristics related to variations in the thickness of the top silicon layer.
The present invention provides a method of producing a SOI MOSFET which includes a fully depleted channel region of a first conductivity type formed in a top semiconductor layer disposed on an insulative substrate, source/drain regions of a second conductivity type formed to sandwich the channel region and a gate electrode formed on the channel region with intervention of a gate insulating film, the method comprising:
forming the channel region by setting an impurity concentration of channel edge regions of the channel region adjacent to the source/drain regions higher than an impurity concentration of a channel central region of the channel region, and setting a threshold voltage Vth0 of the channel central region and a threshold voltage Vthedge of the channel edge regions so that a change of the threshold voltage Vth0 with respect to a change of the thickness of the top semiconductor layer and a change of the threshold voltage Vthedge with respect to the change of the thickness of the top semiconductor layer are of opposite sign.
That is, in view of the above-described problems, an object of the present invention is to provide a method of producing a highly reliable SOI MOSFET by effectively reducing the short-channel effect, the punch through and the like and suppressing the influence of the thickness of the top semiconductor layer on the electrical characteristics of the SOI MOSFET, and such a highly reliable SOI MOSFET.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.